Tuesday, October 7, 2014
7 Set Question of "COMPUTER ARCHITECTURE"
x'z'+y'z'+yz'+xy
2. The width of the bus is 2 bits, calculate
- Size of the register
- How many multiplexer that must be used for the bus construction? How many input leg output log for a multiplexer
- How many Decoder that must be used for the bus construction? How many input leg output log for a multiplexer
- Draw the diagram showing the connection between all the device
3. Explain and draw the block of diagram bus Transfer of the basic computer below
- The bus selected 2 devices source and destination
- Selected device give the data to the bus (Bus < Reg)
- Selected device destination recieved
| Destination | Received | ||
|---|---|---|---|
| S2 | S1 | S0 | Source Device |
| 0 | 0 | 0 | no selection |
| 0 | 0 | 1 | AR |
| 0 | 1 | 0 | PC |
| 0 | 1 | 1 | DR |
| 1 | 0 | 0 | AC |
| 1 | 0 | 1 | IR |
| 1 | 1 | 0 | TR |
| 1 | 1 | 1 | Memory |
4. Construct the Arithmetic circuit which work as in the given functions in the table below, all the information will be used for the circuit construction
Draw your Arithmetic circuit
| S1 | S0 | cin | y | output | Microoperation |
|---|---|---|---|---|---|
| - | - | - | - | D=A+Bi | Subtract with borrow |
| - | - | - | - | D=A+Bi+1 | Subtract |
| - | - | - | - | D=A+B | Add |
| - | - | - | - | D=A+B+1 | Add with carry |
| - | - | - | - | D=A+1 | Increment A |
| - | - | - | - | D=A | Transfer A |
| - | - | - | - | D=A-1 | Decrement A |
5. figure image below
- How many conditions that effect to the Data Register? list all of them
- How many conditions for loading data into DR? list all of them
- How many conditions for Increment data into DR? list all of them
- How many conditions for clearing data DR? list all of them
- Draw the logic diagram for control signals of the DR
6. Image figure below
- How many conditions For E Register? list all of them
- What is the equation for log J of the flip flop?
- What is the equation for log K of the flip flop?
- Draw the diagram for generating the control signals for E register using the following figure
7. Construct the diagram for controlling the selection of the common bus when the memory is selected as the source
| X1 | X2 | X3 | X4 | X5 | X6 | X7 | S2 | S1 | S0 | Selected register |
|---|---|---|---|---|---|---|---|---|---|---|
| - | - | - | - | - | - | - | - | - | - | None |
| - | - | - | - | - | - | - | - | - | - | AR |
| - | - | - | - | - | - | - | - | - | - | PC |
| - | - | - | - | - | - | - | - | - | - | DR |
| - | - | - | - | - | - | - | - | - | - | AC |
| - | - | - | - | - | - | - | - | - | - | TR |
| - | - | - | - | - | - | - | - | - | - | TR |
| - | - | - | - | - | - | - | - | - | - | Memory |
- The list of machine code is for and addition of two number
- Translate the binary machine code to the equivalent hexadecimal
- Show the list code using OP.code symbol and explain the action of the OP.code
- What is the final result of the execution
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